Combined content addressable memories

ABSTRACT

A method and circuit for a high speed interface that enables the integration of several Content Addressable memories into a larger, Combined Content Addressable Memory with only an insignificant delay in the original response time of the individual memories. The interface provides connections to the Bus system only and no connection between different CAM devices of the system is needed, whereby the combination of one CAM and one CAM interface in a single device, such as a chip is enabled. Such chips may be used as modules for increasing the CAM Memory by directly attaching them to the Bus System without any additional interface, as known for standard memory chips such as RAM. The inventive interface may also be used for creating, a hierarchical structure within a CAM device by dividing the memory cells in groups each group being interfaced to the larger combined CAM device via an interface according to the invention. In such a structure the priority function in each group operates on a smaller number of cells and due to the relatively small number of gates necessary for making the interface the implementation of a CAM device with a reduced number of gates is facilitated. In a combined CAM device several CAMs are connected to an Address Bus and to a Data Bus via their respective interfaces. In the Read and Write mode the interface will connect the two sets of lines and thus be transparent for the Read or Write operation. In the search mode (Content Addressing mode), the Interface will select and set a number of lines of the Data Bus according to the CAM response so as to output the address of one matching cell that is the highest in a predefined direction. The interface circuit adds the logic functions and lines necessary to expand the Content addressable functions of the CAM module to a larger range of addresses, sets an additional number of bus lines in order to write the address of the cell within that larger range and checks that no other cell with a higher address responds throughout the system by masking the bits of the CAM address if they would change the address of a cell with a higher address. In this way the whole ensemble of CAMs is capable of functioning as a single CAM of larger size.

FIELD OF THE INVENTION

[0001] The present invention relates to a method and circuit for ahigh-speed interface that enables the integration of several ContentAddressable Memories into a larger, Combined Content Addressable Memory.

[0002] In the framework of the invention, the term Content AddressableMemory (CAM) will generally refer to a memory device having, in additionto the normal Store and Retrieve functions of a memory, a contentaddressing function the operation of which may be described as follows:

[0003] When a Content Addressable Memory device is placed in the ContentAddressing mode, a given value is set on a number of Bus Interfacelines, and the device responds by setting on another set of BusInterface lines data representing the position of one memory cell. Thatcell, designated hereinbelow the Responding Cell, has stored dataverifying a predefined relationship with the data presented on the firstBus Interface Lines (hereinbelow designated Matching Data). In sometypes of CAMs, the first and second set of Bus Interface Lines may bethe same physical lines, used in both the above phases of the operatingcycle. The first and second set of Bus Interface Lines will bedesignated hereinbelow Address Bus and Data Bus.

[0004] Memory devices of the above type are described for example inpatents U.S. Pat. No. 4,805,093, U.S. Pat. No. 5,502,832 and U.S. Pat.No. 5,568,416.

[0005] In the framework of the present invention, CAM will also refer toCall Out Memories of the types described in Patents PCT/IL 00/00121 andPCT/IL 00/00327. Call Out Memories may also have a “Range” functiondefining an address value for which the term “Origin Address” will beused. The Origin Address may be transferred as an input to the Call OutMemory.

[0006] In the content addressing mode this Origin Address defines astarting position for the search function, in a given direction, and thesearch may be defined so that the Address Output of a Call Out Memory isthe biggest, but smaller than the Origin Address, in a predefineddirection, among all Memory Cells having matching data. In case of CallOut Memories the Content Addressable mode is also referred to as CallOut mode.

[0007] Existing CAM devices have limited capacity, due to the largenumber of gates necessary to implement them. As a result, where a largeContent Addressable Memory space is needed, a plurality of CAM devicesmust be used. However merging many CAMs into a larger ContentAddressable Memory requires dedicated interface or connections. Suchinterface circuit will in turn cause delays, resulting in a longerresponse (search) time for the overall Content Addressable Memory.

[0008] Various methods have been proposed for cascading CAMs in amodular way (WO99/23662, U.S. Pat. No. 5,930,359), however these methodsimply a degradation in response time. Thus for example in the case ofU.S. Pat. No. 5,930,359 the searched result is pipelined through all theCAMs, thereby causing a potential delay in the final response, to bemultiplied by the number of CAMs. In WO992362 an improved system isshown, in which only a logical signal is passed from CAM to CAM, thusresulting in a delay equal to elementary gate delay multiplied by thenumber of CAMs.

[0009] In both cases, the integration of several CAMs in a single largeContent Addressable Memory causes degradation in response time of thememory.

[0010] Another disadvantage of these integrating methods is that theparallel architecture of the Bus System is violated becauseinterconnections between different CAM devices must be provided. This inturn degrades system modularity and expandability.

[0011] It is therefore desirable to design a modular interface for a CAMdevice that does not add delay and at the same time preserves theparallel architecture of the BUS system. It is further desirable todesign a modular interface for a CAM device that is integrallyconstructed with the CAM device such that the combined CAM and interfacemay be applied as a modular unit for fast and simple enlargement of anexisting memory without the need for the addition of further circuitry.

[0012] It is also desirable to design a modular interface for a CAMdevice that enables the construction of large and complex CAM deviceswhile reducing the number of logic gates and the amount of wiringnecessary for such structures.

SUMMARY OF THE INVENTION

[0013] A method and circuit for a high speed interface that enables theintegration of several Content Addressable memories into a larger,Combined Content Addressable Memory with only an insignificant delay inthe original response time of the individual memories.

[0014] The novel interface provides connections to the Bus system onlyand no connection between different CAM devices of the system is needed,whereby the combination of one CAM and one CAM interface in a singledevice, such as a chip is enabled. Such chips may be used as modules forincreasing the CAM Memory by directly attaching them to the Bus Systemwithout any additional interface, as known for standard memory chipssuch as RAM.

[0015] The inventive interface may also be used for creating ahierarchical structure within a CAM device by dividing the memory cellsin groups, each group being interfaced to the larger combined CAM devicevia an interface according to the invention. In such a structure thepriority function in each group operates on a smaller number of cellsand due to the relatively small number of gates necessary for making theinterface the implementation of a CAM device with a reduced number ofgates is facilitated.

[0016] In a combined CAM device several CAMs are connected to an AddressBus and to a Data Bus via their respective interfaces. In the Read andWrite mode, the interface will connect the two sets of lines and thus betransparent for the Read or Write operation. In the search mode (ContentAddressing Mode), the Interface will select and set a number of lines ofthe Data Bus according to the CAM response so as to output the addressof one matching cell that is the highest in a predefined direction. Theinterface circuit adds the logic functions and lines necessary to expandthe Content addressable functions of the CAM to a larger range ofaddresses, sets an additional number of bus lines in order to write theaddress of the cell within that larger range and checks that no othercell with a higher address responds throughout the system by masking thebits of the CAM address if they would change the address of a cell witha higher address. In this way the whole ensemble of CAMs is capable offunctioning as a single CAM of larger size.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIG. 1 shows the general arrangement of an Interface for a CAMdevice according to the invention.

[0018]FIG. 2 shows how several CAMs can be integrated in one larger CAMby coupling each CAM with a CAM interface of the invention.

[0019]FIG. 3 shows how several CAMs can be grouped to form larger CAMs,these CAM groups also being interfaced according to the invention, thusforming a still larger CAM memory.

[0020]FIG. 4 shows the components of a CAM interface according to theinvention.

[0021]FIG. 5 shows how priority masks are connected in a “OR” functionto the Data Bus.

[0022]FIG. 6 shows an example of implementation for the Priority Mask.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0023] It is the object of the present invention to provide a high speedinterface that enables the integration of several Content AddressableMemories into a larger, Combined Content Addressable Memory. Inaccordance with the inventive method and circuitry, the new interfaceprovides connections to the BUS system only, and no connection betweendifferent CAMs within the same system is needed. The inventive interfaceis advantageous in that the delay added by the interface is very small,and not dependent on the number of CAMs installed. Thus the novelinterface integrates all installed CAMs in one Content AddressableMemory of larger size, having a response time almost equal to that of asingle CAM device.

[0024] The inventive interface may also be used to interconnect memoriesof the Call Out type. These memories are designed to operate in either aR/W mode or a Call Out mode. A Call Out Memory comprises a Range Circuitand when in the Call Out Mode, it will output on the Bus the Address ofa Matching Cell with the highest value in a predefined direction butlower than an Origin Address. Such memories have been described inPCT/IL 00/00121 and PCT/IL 00/00327.

[0025] The following example may best demonstrate the interface of theinvention. Where an available CAM device comprises 2^(W1) elementarycells, each cell capable of storing Wd bits, the novel interface willprovide means to integrate up to 2^(w2) identical CAMs in order tocreate a CAM memory comprising 2^(w1+w2) cells. In this example, all theCAM devices have the same size, i.e. the same number of cells, but theinvention can also provide interface for several CAM devices, ofdifferent sizes.

[0026] It is an advantage of the invention that the resulting largerContent Addressable Memory array will function at almost the same speedas each individual CAM. Only a minimum delay is added.

[0027] In accordance with a further advantageous feature of theinventive method and circuit, the interface designed according to theinvention will provide a modular interface, having connections to theCAM module and the Bus System only, i.e. no connection to the other CAMsof the system is needed. This feature makes possible the combination ofone CAM and one CAM Interface in a single device, such as a chip.Several devices or chips of that type may then be directly used in theBus System, without any additional interface, in the same way known forthe addition of several standard memory chips (for example Random AccessMemory) to a Bus System to form a larger memory.

[0028] It is yet another advantageous feature of the invention that aninterface designed according to the invention can be used to create ahierarchical structure within a CAM group being interfaced to the largerCAM device by means of an interface according to the invention. Usingsuch architecture, the number of logic gates needed to implement the CAMcan be reduced, because the priority function in each group operates ona smaller number of cells. The number of gates necessary to make theinterface is relatively small, since only one such interface needs to beprovided for all the cells in one group. Due to the above enumeratedadvantages of the invention, the implementation of a CAM device with areduced number of gates is facilitated.

[0029] Where the Interface of this invention is used to interface CallOut memories, an Origin Address interface is also provided. Theinterface will receive an Origin Address from the System Bus, and willenable the CAM only if at least one cell of the CAM has a lower address(in a predefined direction) than the Origin Address.

[0030] The invention will be described hereinbelow in respect of apreferred embodiment. It will be understood however that many variationsand modifications of the inventive interface and circuit may be madethat still remain in the scope of the invention as described and claimedherein.

[0031] Referring to FIG. 1, a CAM memory is shown with an Interfaceaccording to the invention. The Interface is connected to the AddressBus via a number Wa of Address lines. The CAM is connected to theInterface via a number Wb of Address Lines, Wb being smaller or equal toWa. The number of lines Wb is the number of address lines needed for theoperation of the CAM device, according to its specifications.

[0032] The Interface is also connected to a Data Bus on one side, and tothe CAM device bus lines on the other side. During the Reading orWriting of values from or to the CAM device, the Interface will connectthe two sets of BUS lines, and will thus be transparent for the Read orWrite operation. When functioning in the search mode (Content Addressingmode), the Interface will select and set a number of lines of the DataBus, according to the CAM response, in order to output on the Data Bus avalue representing the position (Address) of one matching cell of theCAM, provided that this matching cell of the CAM is the one having theHighest address in a predefined direction, among all cells of all CAMspresent in the system.

[0033] A number of Select Lines are connected to the interface, used todefine the specific position of the CAM and CAM Interface in the totaladdress space of the Bus System. Such Select Lines are commonly used inBus Systems to define the position of a device having a restrictedaddress space. Typically the Select Lines will be fixed to predefinedlogic levels, thus defining the address range of the CAM cells in thetotal memory range of the system.

[0034] An additional set of Control Lines of the System Bus, is alsoconnected to the interface, and from the interface to the CAM device.The Control Lines from the System Bus to the interface are designated inFIG. 1 Bus Control Lines and the Control Lines from the interface to theCAM device are designated Interface Control Lines. Such control lines,carrying the signals required for the implementation of the Busprotocol, are of common use in Bus systems.

[0035] A CAM that is installed within a larger CAM device and connectedvia the inventive CAM interface will be designated herein a CAM module.

[0036] The purpose of the interface circuit is to add the logicfunctions and lines necessary to expand the Content Addressablefunctions of the CAM module to a larger range of addresses. The CAMmodule, having been designed for a limited size, is able to output theaddress of one of its Responding Cells with a smaller number of bitsthan the number of bits necessary to define an address in the wholesystem. Upon integrating the CAM module in a larger Content AddressableMemory, it becomes necessary to set an additional number of Bus lines inorder to write the address. Furthermore, it will be necessary to check,before the Address is put out, that no other cell with a higher addressresponds throughout the system. The CAM Interface will then. a)_set theadditional Bus Lines in order to write the extended Responding CellAddress, b)_mask the bits of that Address if they would change theAddress of a responding cell with a Higher Address.

[0037] For example, a large CAM array may be designed by integratingseveral CAM devices, each containing 2^(w1) cells. Each of these CAMdevices will put out w1 lines to set the Address Value of theirrespective single matching cells. The larger system, formed by a number2^(w2) of CAM devices will require w1+w2 lines to put out Addressvalues. The role of the interface will then be to interface the w1 linesof the CAM and appropriately set the w2 lines connected to the Data Bussuch that the whole ensemble of CAM modules will function as a singleCAM of larger size.

[0038] In FIG. 2, it is shown how several CAM devices can be integratedto form one larger Content Addressable Memory. CAMs and CAM Interfacesare grouped in elementary CAM blocks, each elementary CAM blockconsisting of a CAM module and a CAM Interface. No interconnectionsbetween elementary CAM blocks are necessary; each elementary CAM blockis connected to the system BUS only. This illustrates the advantage ofthe inventive CAM interface over the prior art.

[0039] With CAMs of the prior art, in order to cascade several CAMmodules within a larger CAM array, interconnections between the CAMmodules are necessary. As a result, it is not possible to enlarge a CAMarray in a modular way.

[0040] By connecting a CAM device to a CAM Interface in accordance withthe novel design of the present invention, several CAM modules can bemodularly aggregated to form a larger CAM array. This is done in thesame way that several common memory devices, such as RAM, are added to aBus System, without adding or changing any of the corrections within theBUS System.

[0041] If for example, the CAM Interface is implemented integrally withthe CAM device (for example in the same chip), then a new CAM element isobtained, that has the same modularity as standard memory devices, forexample RAM.

[0042] In FIG. 3, a hierarchical organization is shown of CAMs and CAMInterfaces that can be used to create a large CAM. Each of theindividual elementary CAM blocks A1, A2, An is designed for a reducedaddress space, so that the number of bits required to describe theaddress is reduced, and the number of logic gates used is also reduced.These individual CAMs are then connected in two groups A and B by meansof CAM Interfaces (A1 to An for group A, B1 to Bn for group B) thatinterface the said CAMs to Group Buses A and B respectively whereby twolarger CAMs are achieved. These two larger CAMs are then connected tothe System Bus by means of two additional CAM Interfaces G1 and G2 andthe two composite CAM blocks each comprising one of the said larger CAMsand one of the Interfaces G1 and G2 are combined into a CAM of evengreater size. Though this example shows only two Composite CAM Blocks,it must be understood that any number of Blocks may be used, and thesame principle operates in the reverse direction, i.e. every sub-groupmay contain several smaller sub-groups, and so on. Such a hierarchicalarchitecture can be used within one device (such as a chip) to achieve alarge size CAM.

[0043] For the purpose of this hierarchical organization, an additionaloutput is provided at each CAM interface. This output (match) isactivated if at least one memory cell of the interface CAM is foundmatching.

[0044] In case that several CAM modules are gathered in one group inorder to be interfaced to a CAM interface at a higher hierarchy, an ORfunction, designated H in FIG. 3, is applied to all these Match lines.The output of that OR is then connected to the CAM interface that ishigher in hierarchy. This signal is then used to selectively activatethe Higher hierarchy Interface if at least one cell among all cellsinterfaced in the lower hierarchical group is matching.

[0045] In FIG. 4, a block diagram of a preferred embodiment for a CAMInterface that is designed for a Call Out Memory is shown, comprisingthe following components:

[0046] a) Chip Select: a logic circuit commonly used in Bus Systems thatenables a device to be activated. In the inventive interface the ChipSelect is used in the Normal Mode, in order to activate the CAM for reador write operation.

[0047] b) Block Range Circuit: The Range Circuit is a comparator circuitthat compares, when the interface is in the Content Addressing mode, thedata set on the Address Bus lines to the Data set on the Select Lines.If the first one is smaller or equal, in a predefined direction, thenthe Block Select signal is issued, that enables the CAM device. AControl line (CO) is also input to the CAM for selectively operating theCAM in the Content Addressing mode.

[0048] c) CAM device: In the scope of this invention, a CAM device willgenerally designate a memory device having, in addition to the normalStore and Retrieve Functions of a memory, a content addressing function,described as follows:

[0049] When a CAM device is placed in the Content Addressing mode, agiven value is set on a number of Bus Interface lines, and the deviceresponds by setting on another set of Bus lines data representing theposition of one memory cell. That cell, designated herein as theResponding Cell, has stored data verifying a predefined relationshipwith the data presented on the first Bus Lines, designated herein asMatching Data.

[0050] Data is defined herein as the number of bits necessary to make abinary representation of the address of a cell inside the CAM device.

[0051] The CAM Interface receives W2 select lines, that define a baseaddress for all cells of the CAM. The address of a cell of the CAM inthe whole system will then be a binary number with Da least significantbits, and W2 most significant bits.

[0052] The CAM device receives as inputs the R/W signal to selectbetween normal Read and Write mode, and the CO line to select betweenNormal and Call Out mode. Additional control lines commonly used inmemory devices are also input to the CAM to enable its normal function.The CAM is enabled by the Chip Select when in normal mode, or by theRange Circuit in the Call Out mode.

[0053] In normal Read or Write operation, Da+Db Data bus lines areconnected to the CAM device through a pair of buffers. Da+Db is the(maximum) number of bits used by the CAM for Read or Write operation.

[0054] In the Call Out mode, only Da lines are buffered to the Data Bus,and used to set a partial Address of the responding cell on the DataBus. This partial address is the Address of the responding cell in theCAM device. The Block Priority Mask will then set the rest of theAddress, according to the W2 select lines, that represents the positionof the CAM device in the total memory system. We shall further refer tothe data set on these W2 lines as the Block Address.

[0055] d) Block Priority Mask: Addresses containing the same W2 mostsignificant bits of the W2 lines (Block Address) are allocated to allthe cells within a CAM device.

[0056] The Block Priority Mask is designed to set these W2 mostsignificant bits if one cell of the CAM is responding, while masking theset bits of any other Address that would change the Address set on theBus, if the Address set on the Bus has a bigger value.

[0057] To implement this function, the Block Priority mask receives asinput the Data Bus lines and the W2 Select lines. By means of a logicfunction on these inputs, the Block Priority Mask will enable for outputonly bits of the Block Address that would not change an address of ahigher value than its own Block Address.

[0058] The Block Priority mask is enabled if the Call Out mode isactivated and one of the CAM cells is responding. If the Block PriorityMask does not detect on the Data Bus any address higher than its ownBlock Address, then it will output the enabling signal to the firstbuffer that will then allow the Address of the responding cell to be putout on the Data Bus.

[0059] e) a Match Detect circuit, which may be a part of the CAM or alogic circuit added to the CAM. Most CAM devices provide a Matchdetection output. This output is activated if at least one cell of theCAM is responding. In the present embodiment, this output is used toenable the Block Priority mask.

[0060] f) a Gate arrangement (Gate 1) that performs the followingfunctions:

[0061] _enable the Block Priority Mask only in the Content Addressingmode.

[0062] _enable the Block Priority Mask only in the event that one cellhas matching data.

[0063] g) Buffers 1 and 2 Buffer 1 is used to connect or isolate Dalines of the data bus from the CAM. This Buffer receives an enablingsignal from an “OR” gate, (gate 3). When the enabling signal is issued,the Buffer performs a connection between Da Data Bus lines and the CAMbus lines.

[0064] Buffer 2 is used to connect or isolate D1b lines of the data busfrom the CAM. It receives CO as a disabling signal. When CO is active,Buffer 2 isolates Db lines of the CAM from the Data Bus.

[0065] If the CAM alone were connected to the Bus system, then Da+Dblines of the CAM would be connected to the Data Bus. In the read orwrite mode, these lines would be used to transfer the data to beretrieved or stored.

[0066] Where the CAM is combined with the inventive CAM Interface, innormal Read/Write mode (CO signal not active), all of the Data Bus linesneed to be connected to the memory cells to perform the usual Read/Writeoperations. Buffer 1 and 2 of the CAM Interface will then be activatedto connect the Data Bus lines to the CAM. Referring to FIG. 4, it willbe observed that the CO signal is input to an “OR” gate (gate 3), thatoutputs an enabling signal to Buffer 1 if CO is not activated. It isfurther shown in FIG. 4 that the signal CO is directly input to Buffer2, enabling that buffer if CO is not activated.

[0067] In Call Out mode, the CAM sets the address of the responding cellon a restricted number Da of lines. Db lines of the CAM are then notused. These lines are disconnected from the Data Bus by Buffer 2.

[0068] If one cell of the CAM is responding, then the CAM will set theaddress of the CAM on Da lines, and the Block Priority Mask will beactivated. The Block Priority mask will set the Block Address on theData Bus on the W2 lines, and this in case that there is no otherresponding cell at a higher address. In that case the Block PriorityMask will also output an enabling signal to Buffer 1, thus allowing theCAM to output the address of the responding cell on the Da leastsignificant bits.

[0069] If the Block Priority Mask detects that an address with highervalue than its own address has been set on the Data Bus, then it willnot output the enabling signal to Buffer 1, so that the CAM will stayisolated from the Data Bus.

[0070] It will be understood that the single CAM shown in FIG. 4 may bereplaced by a unit of higher complexity such as an Elementary CAM blockor a Composite CAM block as described in reference to FIG. 2 and theinventive interface may enable the read and write and call out functionsin respect of that complex unit in a similar manner.

[0071]FIG. 5 shows the connection between a Block Priority Mask and theData Bus. On one side of the Block Priority Mask the Data Bus lines areconnected as input while on the other side of the said Block PriorityMask each output line of the Block Priority Mask is connected by a wide“Or” to the Data Bus.

[0072]FIG. 6 shows a preferred embodiment for the priority mask. TheBlock Address is represented in FIG. 6 in the form: $\begin{matrix}{{{Block}\quad {{Address}:\quad N}} = {\sum\limits_{k = 0}^{K}\quad 2^{\lbrack{u{({N,k})}}\rbrack}}} & (1)\end{matrix}$

[0073] Where:

[0074] K is the number of set bits in the Block Address minus 1.

[0075] u(N,k) is the position of the k-th bit in the Block Address,relative to least significant.

[0076] For example, to interface a CAM having 16 (4 bits) memory cellsinto a larger CAM having 256 (8 bits), the Block Address will contain 4bits.

[0077] The Block Address will then have an address containing the 4 mostsignificant bits, then all least significant bits zero:

[0078] For example N=1010,0000

[0079] The Number of set bits is 2, so K=1

[0080] We may write 10100000=1.2⁷+1.2⁵

[0081] So in this case we have:

[0082] U[N,0]=5; U[N,1]=7;

[0083] Referring again to FIG. 6, for every set bit of the BlockAddress, a line P{N,u(N,k)} is output from the Block Priority Mask.

[0084] The state of that line is set by a logical gate, and it will beset to Active (Logical 1) if all the following conditions are verified:

[0085] a)_At least one cell of the CAM is responding, thus activatingthe Enabling signal E.

[0086] b)_The state of the next line at a more significant bit positionis active (logical 1), or if the present line is at the most significantbit.

[0087] c)_The state of all Bus lines of bits between the present linebit position and the next line at a more significant bit position is notactive.

[0088] a Block Match signal is issued if P[N, u(N,O)] is active and thestate of all Bus lines at bits of the Block Address of less significantposition than P[N, u(N,O)] is not active. In case there are no suchlines, then the Block Match line will be activated by P[N, u(N,O)]directly.

[0089] Where the Block Priority Mask does not have any P(k) lines,(Block Address=0), then the Block Match signal I output when the enablesignal is activated.

[0090] The purpose of this logical circuit is to Mask, i.e. not to set,a bit of the Data Bus if it would change the partial address already seton more significant bits of the Data Bus.

[0091] This example shows a particular implementation, but obviouslymany implementations of the Priority Mask are possible, all having thesame principle according to which the line P[N,u(N,k)] is masked (i.e.maintained inactive), if one or more lines of more significant bits ofthe Data Bus are active, at positions where the Block Address has unsetbits.

1. A CAM interface that enables the integration of two or more CAMdevices into a composite CAM array by connecting the CAM devices to thesame Data bus lines and to the same Address bus lines, comprising: a) aplurality Wa of lines connecting the CAM interface to a number ofAddress bus lines and a plurality of Wb lines connecting the CAMinterface to the CAM device wherein Wa is larger or equal to Wb; b) afirst buffer for selectively connecting a first plurality Da of Datalines of the CAM to the same number of Data lines of the Data bus, theconnection being done when a first enabling signal is set; c) a secondbuffer for selectively connecting a second plurality Db of data lines ofthe CAM to a second number of data lines of the data bus, the saidsecond number of Data lines being equal to Db, the said connection beingdone when a second enabling signal is set; d) and a Priority MaskCircuit that receives as input a plurality W2 of Select Lines, thestates of which define a Block Address for the CAM interface and alsoreceives as input an enabling signal, the said Priority Mask circuitbeing further connected to a Data Bus via a number W3 of Data Lines, W3being larger or equal to W2 wherein if a number or at least one of thememory cells within the CAM have stored data verifying a givenrelationship with the data set on the Address Bus lines, then the CAMselects one of the said number of cells, according to the internalpriority order defined for the CAM, and applies the address of that cellon the said first buffer or the CAM applies the address of the singleresponding cell on the said first buffer; the CAM also outputs the saidenabling signal to the Block Priority Mask; the Block Priority Masklogic circuit then applies the said Block Address on the said W3 numberof Data Bus lines while masking any bit of that address that wouldinterfere with any Address being Higher in a predefined direction thathas been set on the said Data Bus lines; and in case that no HigherAddress was output on the Data Bus, the Block Priority Mask logiccircuit outputs the said first enabling signal to the said first buffer,whereupon the selected address is set to the said first number of DataBus lines.
 2. A CAM interface according to claim 1 hereinabove whereinthe same bus lines may be alternatively used as address bus lines anddata bus lines in accordance with the function requirements of thesystem.
 3. A CAM interface according to any of claims 1 or 2 hereinabovethat also comprises a Block Range Circuit for comparing an address seton the Address Bus to the Block Address and enables the CAM only in casethat the Block Address is lower or equal in the predefined directionthan the address set on the Address Bus.
 4. A block priority mask and ablock address, the said block address being the address of a CAM memorydevice within a composite memory array with two or more memory devicesinterfaced to the same Data bus lines and the same Address bus lines,characterized in that the said block priority mask has one enablinginput line, one output line P(k) for every bit set k of the said blockaddress and one block match line wherein the said block priority maskreceives as input the said data bus lines and when enabled it performs alogical function that activates each of the said output lines P(k) ifand only if no other device on the Data bus has already set a line at amore significant bit position at which the block address has an unsetbit and wherein the Block Match line will be activated if (a) all P(k)lines are activated and (b) there is no other Bus line activated at anybit position of the block address,if that Bus line is at a lesssignificant bit position than the P(k) with the least significant bitposition.
 5. A block priority mask as claimed in any of claims 3 or 4hereinabove wherein according to the said logical function the state ofP(k) is set to Active (Logical 1) if all the following conditions areverified: a)_At least one cell of the CAM is responding, thus activatingan Enabling signal. b)_The state of the next line at a more significantbit position is active (logical 1), or the present line is at the Mostsignificant bit position. c)_The state of all Bus lines of bits betweenthe present line bit position and the next line at a more significantbit position is not active; and a Block Match signal is issued if theP(k) line at the least significant bit position is active and the stateof any Bus lines at bits of the Block Address of less significantposition than the said P(k) line is not active.
 6. A Block Priority maskwith a logical circuit as claimed in claim 5 hereinabove wherein thePriority Mask does not have any P(k) lines (Block Address=zero) and theBlock Match signal is output when all Bus lines at positions of theBlock Address are not set.
 7. A hierarchical CAM architecture whereintwo or more CAMs are integrated into a group and two or more groups areintegrated into a composite memory array or two or more composite CAMmemory arrays or a composite CAM memory array and a single CAM areintegrated into a larger composite CAM memory array characterized inthat each of the CAM devices respectively has a CAM interface in whichan additional output connection is provided and this output is activatedif at least one memory cell of the interfaced CAM is found matching; anOR function is applied to the said output lines of the said CAM unitsand the said OR function is corrected to the CAM interface that is nextand higher in hierarchy whereby this output signal selectively activatesthe said higher hierarchy interface if at least one cell among all cellsinterfaced in the said lower hierarchy group of CAMs is matching.
 8. Ahierarchical architecture for a CAM memory as claimed in claim 7hereinabove for dividing a large composite CAM memory array into smallerCAM units or groups each of which may be searched separately or left outof a search cycle as necessary.
 9. A hierarchical architecture for a CAMmemory as claimed in claim 7 hereinabove that is integrated within adistinct device such as a chip.
 10. A hierarchical architecture asclaimed in any of claims 7 to 9 hereinabove that may be added as amodule to a CAM memory comprising the interface of claim 1 in order toenlarge the said CAM memory.
 11. A hierarchical architecture as claimedin any of claims 7 to 10 hereinabove in which an origin address for thememory search may be fed into one or more of the CAM units whereby theaddress that is put out on the bus lines as a result of the search mustverify a predefined relationship with the said origin address.
 12. A CAMinterface substantially as described herein with reference to thedrawings.
 13. A hierarchical architecture for a CAM memory substantiallyas described herein with reference to the drawings.